FIG. 1 (Prior Art) shows a 5 volt digital inverter 1 with hysteresis. Hysteresis is commonly used to reduce sensitivity to noise on input signals of a circuit and/or to control the propagation delays of signals passing through a circuit. In this example, when the output voltage V.sub.out supplied on output terminal 2 of inverter 1 is approximately 5.0 volts (i.e., a logic 1), V.sub.out will not transition to approximately 0 volts (i.e., a logic 0) unless the input voltage V.sub.in on input terminal 3 is increased to 2.6 volts or greater. The threshold voltage necessary during a transition from a logic 0 to a logic 1 on input terminal 3 to begin switching V.sub.out from a logic 1 to a logic 0 is hereinafter referred to as V.sub.T01. In this example, V.sub.T01 is 2.6 volts.
On the other hand, when V.sub.out is at a logic 0, V.sub.out will not begin switching to a logic 1 unless voltage V.sub.in is 2.4 volts or lower. The threshold voltage necessary during a transition from a logic 1 to a logic 0 on input terminal 3 to begin switching V.sub.out from a logic 0 to a logic 1 is hereinafter referred to as V.sub.T10. In this example, V.sub.T10 is 2.4 volts.
Digital inverters generally do not have well controlled hysteresis threshold voltages, V.sub.T01 and V.sub.T10. The two hysteresis threshold voltages V.sub.T01 and V.sub.T10 may only be a few tenths of a volt apart and may be at undesirable voltages.
FIG. 2 (Prior Art) shows an idealized non-hysteresis inverter 4 comprising a P-channel field effect transistor (FET) 5 and an N-channel FET 6. P-channel FET 5 has its gate connected to input terminal 7, its source connected to supply voltage V.sub.CC, and its drain connected to output terminal 8. N-channel FET 6 has its gate connected to input terminal 7, its source connected to ground, and its drain connected to output terminal 8. The operation of inverter 4, with no load on output terminal 8, is as follows.
An input voltage V.sub.in present on input terminal 7 causes inverter 4 to generate an output signal V.sub.out on the output terminal 8 according to the hysteresis transfer characteristic illustrated in FIG. 3 as waveform W1.
FIG. 4 illustrates an output characteristic of a field effect transistor. N-channel FET 6 (FIG. 2), for example, will not conduct significant drain current I.sub.D when its gate-to-source voltage V.sub.GS is below its threshold voltage V.sub.TN. This threshold (voltage V.sub.TN) refers to a condition different from the hysteresis threshold (voltages V.sub.T10 and V.sub.T01) described above. V.sub.TN refers to the minimum gate-to-source voltage necessary to accumulate electrons in the P-type semiconductor to create an N-type channel connecting the source and drain. This N-type channel allows the N-channel FET to conduct current. FIG. 4 shows that at a given drain-to-source voltage V.sub.DS, current I.sub.D flowing through the FET increases as V.sub.GS increases.
When the input voltage V.sub.in on the input terminal 7 of inverter 4 of FIG. 2 is a logic 1, V.sub.GS of N-channel FET 6 is equal to V.sub.CC so that N-channel FET 6 is conductive. V.sub.GS of P-channel FET 5, on the other hand, is zero so that P-channel FET 5 is nonconductive. Output voltage V.sub.out on output terminal 8 is therefore a logic 0.
As the input voltage V.sub.in decreases, the magnitude of the gate-to-source voltage of P-channel FET 5 increases. Eventually the magnitude of the gate-to-source voltage of P-channel FET 5 reaches the threshold voltage of P-channel FET 5 where P-channel FET 5 begins to conduct current. N-channel FET 6 is conductive because its V.sub.GS is still approximately V.sub.CC, and will continue to conduct while its V.sub.GS is greater than its V.sub.TN. Current therefore begins to flow from V.sub.CC to ground but is limited by the conductivity of P-channel FET 5. In this condition, V.sub.DS of P-channel FET 5 is approximately V.sub.CC and V.sub.GS is at threshold so P-channel FET 5 is in its saturation region of operation. Because V.sub.DS across N-channel FET 6 is approximately zero volts and because the current through N-channel FET 6 must be the same as the current through P-channel FET 5, N-channel FET 6 is seen to be operating in its linear region of operation. This condition is shown as point 9 in FIG. 3. As V.sub.in is lowered further, the voltage V.sub.out begins to rise as is shown in FIG. 3 by portion 10 of the waveform W1 in FIG. 3.
In the example non-hysteresis inverter 4 of FIG. 2, when the input voltage V.sub.in equals 0.5 V.sub.CC, the gate-to-source voltages on P-channel FET 5 and N-channel FET 6 are equal. Because the drain current I.sub.D through both transistors must be identical, both transistors must be operating at the same location on the V.sub.GS =0.5 V.sub.CC curve in FIG. 4 where V.sub.DS =0.5 V.sub.CC. At this point, shown as point 11 on waveform W1 in FIG. 3, both transistors are in saturation. The input voltage V.sub.in required to drive both FETs into saturation is referred to hereinafter as the inverter's logic threshold voltage, V.sub.TI.
As the input voltage V.sub.in continues to drop, the current that N-channel FET 6 can conduct continues to drop because the gate-to-source voltage V.sub.GS of N-channel FET 6 is reduced. Conversely, the magnitude of the gate-to-source voltage V.sub.GS of P-channel FET 5 is increased. Because the drain current through the two transistors must be identical, P-channel FET 5 enters its linear region of operation whereas N-channel FET 6 remains saturated. As a result, the output voltage V.sub.out continues to increase as is indicated by portion 12 of the waveform W1 in FIG. 3.
As the input voltage V.sub.in is further reduced, the gate-to-source voltage V.sub.GS of N-channel FET 6 decreases below its threshold voltage V.sub.TN. N-channel FET 6 therefore becomes nonconductive. This condition is indicated by point 13 on waveform W1 in FIG. 3.
FIG. 5 (Prior Art) shows a hysteresis buffer circuit 20. The output lead 21 of a first inverter 22 is coupled to the input lead 23 of a second inverter 24 at node N1. A P-channel FET 26 has its gate connected to the output lead 27 of second inverter 24 at node N2, its source connected to the supply voltage V.sub.CC, and its drain connected to node N1. An N-channel FET 29 has its gate connected to the output lead 27 of inverter 24 at node N2, its source connected to ground, and its drain connected to node N1. Hysteresis circuit 20 is useful in applications where only a small amount of hysteresis is sufficient.
FETs 26 and 29 control the hysteresis threshold voltages of the hysteresis buffer circuit 20. When the input voltage V.sub.in on input terminal 30 is static at a logic 1, the voltage on node N1 is static at a logic 0. The output voltage V.sub.out on output terminal 31 is therefore a static logic 1. P-channel FET 26 is therefore turned off and N-channel FET 29 is turned on.
As the input voltage V.sub.in begins to transition downward to a logic 0, P-channel FET 35 begins conducting current. However, because N-channel FET 29 is on at this point due to the output voltage of inverter 24 still being a logic 1, current flows from V.sub.CC through P-channel FET 35 and is conducted to ground through both N-channel FETs 29 and 36.
As the input voltage V.sub.in decreases further, P-channel FET 35 is made to conduct more current because the magnitude of the gate-to-source voltage V.sub.GS of P-channel FET 35 increases. At some point, V.sub.in drops low enough so that N-channel FET 36 stops operating in its linear region and begins operating in its saturation region. Because the current from P-channel FET 35 is divided between N-channel FETs 29 and 36, P-channel FET 35 must conduct more current (i.e., V.sub.in must be lower) than in the previous example explained in connection with FIG. 2 to conduct the combined current conducted by N-channel FETs 29 and 36. Thus, the threshold voltage of hysteresis buffer circuit 20 for high-to-low input voltage transitions (i.e., V.sub.T10 of hysteresis buffer circuit 20) is lower than the 0.5 V.sub.CC threshold voltage V.sub.TI of inverter 4 of FIG. 2. Waveform W2 in FIG. 3 illustrates that for a high-to-low input voltage V.sub.in transition, the input voltage V.sub.in must be lower (see point 40) than 0.5 V.sub.CC to cause the voltage on node N1 to have a voltage of 0.5 V.sub.CC.
A further drop in input voltage V.sub.in causes N-channel FET 36 to conduct less current so that N-channel FETs 36 and 29 together do not conduct the current conducted by P-channel FET 35, thereby causing the voltage on node N1 to transition to a logic 1. Second inverter 24 therefore causes voltage V.sub.out to transition to a logic 0 which in turn causes N-channel FET 29 to turn off and P-channel FET 26 to turn on.
For a low-to-high voltage transition on input terminal 30, the process is similar to that described above. P-channel FETs 26 and 35 are initially conductive and the voltage on node N1 is initially a logic 1. As V.sub.in increases, N-channel FET 36 starts to conduct current. Current flows from V.sub.CC through P-channel FETs 26 and 35 to node N1 and through N-channel FET 36 to ground. Eventually N-channel FET 36 will conduct as much current as P-channel FETs 26 and 35. Because the current conducted by N-channel FET 36 is divided between P-channel FETs 26 and 35, V.sub.in must be higher than required in the inverter 4 of FIG. 2 to cause the voltage on node N1 to be 0.5 V.sub.CC. Waveform W3 in FIG. 3 illustrates that for a low-to-high input voltage V.sub.in transition, the input voltage V.sub.in must be higher (see point 41) than 0.5 V.sub.CC to cause the voltage on node N1 to have a voltage of 0.5 V.sub.CC. Point 41 is the threshold voltage of hysteresis buffer circuit 20 for low-to-high input voltage transitions (i.e., V.sub.T01 of hysteresis buffer circuit 20).
Hysteresis buffer circuit 20 may, however, malfunction. Proper operation of hysteresis buffer circuit 20 depends on the saturation current of each of transistors 26, 29, 35 and 36, which may vary with the manufacturing process. If, for example, N-channel FET 29 is made too large, then on a high-to-low input voltage transition N-channel FET 29 may be able to conduct any current that P-channel FET 35 can provide (N-channel FET 29 will not go into saturation). In this condition, no input voltage V.sub.in could cause the voltage on node N1 to transition from a logic 0 to a logic 1. As a result, the output voltage V.sub.out would not transition despite the input voltage V.sub.in transitioning.
This problem is more likely to arise when a large hysteresis is desired. In hysteresis circuit 20, to increase V.sub.T10, N-channel FET 29 must be made larger. Due to variations in the manufacturing process, making N-channel FET 29 larger increases the probability that the saturation current of N-channel FET 29 will be large enough to cause the malfunction described above. Thus, this problem limits the amount of hysteresis that can be achieved.
Further, because saturation current varies with temperature, hysteresis buffer circuit 20 may also malfunction in the manner described above due to changes in temperature. Thus, hysteresis circuit 20 may operate properly at room temperature but malfunction at a different temperature due to different temperature coefficients between N-channel and P-channel transistors comprising hysteresis circuit 20.
FIG. 6 (Prior Art) illustrates an application for hysteresis buffer circuit 20 in a voltage controlled oscillator 50. Input lead 52 of inverter 51 is coupled to output terminal 31 of hysteresis buffer circuit 20. The output signal of inverter 51 is connected to output terminal 53 and also controls the switching of switch 63. Switch 63 couples either ground potential or variable control voltage V.sub.CONTROL to node N3. Node N3 is coupled to one end of resistor 64, and the other end of resistor 64 is connected to input terminal 30 of hysteresis circuit 20. Capacitor 65 is coupled between input terminal 30 and ground.
Voltage controlled oscillator 50 operates as follows. The voltage across capacitor 65 is the input voltage V.sub.in to hysteresis buffer circuit 20. When voltage V.sub.in is a logic 0 (i.e., node N3 is coupled to ground by switch 63 and capacitor 65 is discharged), V.sub.out at output terminal 53 is at a logic 1. Consequently, switch 63 is controlled to couple control voltage V.sub.control to capacitor 65 through resistor 64. As capacitor 65 charges, voltage V.sub.in increases until V.sub.in reaches hysteresis voltage threshold V.sub.T01 of hysteresis buffer circuit 20. Voltage V.sub.out at output terminal 53 then transitions to a logic 0. This in turn causes switch 63 to decouple voltage V.sub.control from node N3 and to couple node N3 to ground. Accordingly, voltage V.sub.in decreases as capacitor 65 discharges. When voltage V.sub.in decreases to hysteresis threshold voltage V.sub.T01, voltage V.sub.out transitions back to a logic 1. Voltage V.sub.CONTROL can be varied to control the rate at which capacitor 65 is charged and discharged. Increasing voltage V.sub.CONTROL causes the voltage across capacitor 65 to increase more quickly and, hence, to reach voltage threshold V.sub.T01 more quickly.
The hysteresis voltage thresholds V.sub.T01 and V.sub.T10 of hysteresis buffer circuit 20 are two of the parameters controlling the frequency and duty cycle of the signal V.sub.out output by voltage controlled oscillator 50. However, the shortcomings of hysteresis buffer circuit 20 described above make it undesirable to use in such applications. Voltage controlled oscillator 50 also has a high power dissipation because each transition of an inverter in voltage controlled oscillator 50 dissipates power.